The present invention relates generally to multi-processor computer systems and more particularly to crossbar switch architecture.
High performance, multi-processor systems with a large number of microprocessors are built by interconnecting a number of node structures, each node containing a small number of microprocessors. This necessitates an interconnection network that is efficient in carrying control information and data between the nodes of the multi-processor.
In the past, crossbar switches, which route communications between the xe2x80x9cnodesxe2x80x9d of a network, included logic for determining a desired destination from message header, and for appropriately routing all of the parallel bits of a transmission; e.g., 64 bits in parallel for a 64 bit microprocessor. A configuration such as this presents inherent scalability problems, principally because its number of nodes or ports limits each crossbar switch. For example, a typical crossbar switch might service four nodes in parallel, and route 64 bits to one of the four nodes; if more nodes were desired, multiple crossbar switches would be cascaded to support the additional nodes. Such a configuration is not readily scalable either in terms of bandwidth; i.e., such a system could not readily be reconfigured to handle 128 bits in parallel to support higher-performance systems, or because the more cascaded structures, the greater the routing overhead and associated latency.
Thus, a method or architecture has been long sought and long eluded those skilled in the art, which would be scalable and re-configurable while having low latency. The system would be packet switched and provide a high availability (HA) crossbar switch architecture.
The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node such that one chip can be used to route all 64 bits in parallel for 64 bit microprocessors or 128 bits in parallel for a 128 bit processor.
The present invention provides a flexible structure that allows dynamic programming of its data routing, such that one commercial crossbar system can support many different network architectures. With dynamic scalability, if nodes are added to an existing system, then different programming may be used to reconfigure the crossbar switches.
The present invention provides a multi-processor system interconnection network based on a scalable, re-configurable, low latency, packet switched and highly available crossbar switch architecture.
The present invention further provides a scalable system by parallelizing the interconnection network into a number of identical crossbar switches. This enables implementation of the interconnection network function without pushing the limits of integrated circuit and system packaging technologies. At the same time, the invention provides a method to substantially increase the bandwidth of a multi-processor system.
The present invention further provides a method to re-configure the ports of the crossbar switches so that a smaller number of crossbar switch circuits can provide the required bandwidth when the multi-processor system consists of a small number of node structures, thus reducing system hardware cost.
The invention described also provides for a redundant interconnection network in parallel to the primary interconnection network, thus significantly enhancing the reliability and high-availability of the multi-processor system.